Image Processing in VHDL on FPGAs
Joint Massey University / IEEE NZ Central Section Workshop
4-6 April, 2018
About the workshop
Field Programmable Gate Arrays (FPGAs) are increasingly being used as an implementation platform for real-time embedded image processing applications because their architecture is able to exploit spatial and temporal parallelism. Unfortunately, simply porting an algorithm onto an FPGA often gives disappointing results, because most image processing algorithms have been optimised for a serial processor. Therefore it is necessary to transform the algorithm to efficiently exploit the parallelism inherent within the algorithm. This course introduces a design approach for FPGA based imaging system development, highlighting the significant differences between hardware and software based design. Through lectures and hands-on laboratories, the basic tools for FPGA based development are introduced, and used for implementing a range of fundamental image processing operations.
This workshop would enable participants to:
- understand the concepts behind using FPGAs for image processing
- gain knowledge of the principles underlying the design and implementation of fundamental image processing operations
- obtain hands on experience of FPGA implementation of image processing algorithms
Who should attend?
This course is aimed at engineers and scientists who need to understand basic concepts of FPGAs, and how they may be applied to image processing. It is targeted particularly for those who are entering this field, or are looking at using FPGAs for an image processing application. Participants are expected to have some background in basic electronics, mathematics, and programming. A basic understanding of image processing concepts would be helpful, although prior background in FPGAs is not required.
Method of Instruction
The workshop will consist of a series of well illustrated
lectures that cover the theory, followed by practical hands-on
laboratories. The laboratories will involve implementation of image processing operations
in VHDL on a Cyclone FPGA, and illustrate the techniques for the real-time processing of images.
Workshop dates and venue
4th - 6th April, 2018 (9:00 am - 5:00 pm),
Massey University, Palmerston North Campus.
Full registration: NZ$1200 (discounted to NZ$1000 for IEEE members)
Student registration: NZ$500 (discounted to NZ$400 for IEEE members)
Massey University staff and students: NZ$150
Registration includes costs of computer usage, course materials, handouts, lunches, morning and afternoon teas
Registrations are available here.
- Image processing and FPGAs
- VHDL primer
- Image capture and display
- Simulation and debugging
- FPGA based design and algorithm implementation
- Histogram processing
- Temporal processing
- Filters: convolution and morphology
- Geometric tansformation
- Colour processing
- Blob processing, and tracking
- Fast Fourier transform
Professor Donald Bailey has over 35 years of experience in image processing and machine vision. Over the last 15 years he has conducted extensive research in mapping image processing algorithms onto FPGAs. He is the author of many publications in this field, including the book "Design for Embedded Image Processing on FPGAs."